(1) Field of the Invention
The present invention relates to a non-volatile memory circuit, a method for driving the same, and a semiconductor device using the memory circuit. In particular, the present invention relates to a non-volatile memory circuit which is an element of a reconfigurable LSI in which circuit interconnection information is rewritable after the LSI is manufactured and retainable after power is turned off, a method for driving the same, and a semiconductor device using the memory circuit.
(2) Description of the Related Art
In recent years, new products in the electronics field have been developed with increasing speed. This has shortened the development cycle of LSIs, one of the most important components of electronic products. Developers, who create new LSI-equipped products one after another, are also demanding more functions and higher performance for LSIs. These demands have essentially shortened the product life of LSIs. Developers sometimes request changes in the specifications of LSIs after their design has been determined and manufacturing has begun. In such circumstances, it is also likely that there is not sufficient time to thoroughly check the design of the LSIs. Therefore, hardware and software containing bugs (faults) may be manufactured. Such hardware and software need to be modified.
Because of such demands, reconfigurable LSIs, such as FPGAs (Field Programmable Gate Arrays), whose circuit interconnection information can be modified after being manufactured, are attracting attention. In FPGAs, the circuit interconnection information and setting information, i.e., parameters, etc., in the look-up table (LUT) are stored in an SRAM. An SRAM loses its content when the system is turned off and power is removed. For this reason, when a system is constructed using FPGAs, a non-volatile memory, such as an EEPROM, is provided in addition to the FPGA. Circuit interconnection information and LUT parameters are stored in the non-volatile memory, and each time the system is turned on and power is supplied, they are read out from the non-volatile memory. In such a construction, after being turned on, the system cannot work until it finishes the readout of the circuit interconnection information and LUT parameters from the non-volatile memory. Therefore, such a construction is not suitable for a system which needs to work immediately after being turned on. It is also desirable to manage the power supply for every block in LSIs in order to reduce power consumption. However, in a system such as that described above, i.e., a system in which circuit interconnection information and LUT parameters must be read out each time it is turned on, power cannot be cut selectively for each block. Accordingly, it is difficult to reduce power consumption.
To solve this problem, researchers developed an FPGA with a built-in EEPROM which maintains circuit interconnection information and LUT parameters after power is removed. However, building an EEPROM in an FPGA chip involves a complicated production process and increased production costs. The EEPROM also suffers from slow rewriting operation, that is, it takes a long time for an EEPROM to rewrite data.
More recently, to overcome these problems, researchers suggested the circuit shown in FIG. 20 (T. Miwa et al., Proceedings of Symposium on VLSI Circuits (2001)). This circuit achieves non-volatility by adding two ferroelectric capacitors to a conventional SRAM which comprises six transistors as shown in FIG. 19. The circuit of FIG. 20 comprises first, third, fifth and sixth N-type transistors (951, 953, 955, and 956), second and fourth P-type transistors (952 and 954), which form a conventional SRAM, and first and second ferroelectric capacitors (964 and 965). One of these capacitors is inserted between a first node 962 and a ferroelectric polarization control line 966, and the other is inserted between a second node 963 and the ferroelectric polarization control line 966. The first node 962 and second node 963 are the memory nodes of the SRAM. Before the circuit shown in FIG. 20 is turned off, a predetermined pulse voltage is applied to the ferroelectric polarization control line 966. This causes the two ferroelectric capacitors 964 and 965 to have polarization directions opposite to each other. When the circuit is turned on, the voltage of a power line 960 is gradually increased in a period of μs order or sub μs order. At this time, the voltages of the first node 962 and second node 963 increase gradually as the voltage of the power line 960 increases. One of the ferroelectric capacitors 964 and 965 needs a higher electric charge than the other because of the polarization reversal of the ferroelectric capacitor. This makes the increasing rates of the voltage of the first node 962 and second node 963 different. Once the voltages of the first node 962 and second node 963 become different, the voltages of those nodes change as follows: the voltage of the node which is increased more quickly rises to the supply voltage level of the power line 960, while the voltage of the other node drops to the ground voltage level of a ground line 961 and they stabilize. In other words, a predetermined pulse voltage is applied to the ferroelectric polarization control line 966 before the circuit is turned off, whereby the data stored in the SRAM at this point are maintained as the polarization state of the first and second ferroelectric capacitors 964 and 965. Upon power-up, this enables the SRAM to recall the data that was stored in the memory before the circuit was turned off. After that, the circuit shown in FIG. 20 operates in a manner similar to a usual SRAM, and the first and second ferroelectric capacitors 964, 965 do not directly participate in the reading or writing control of memories.
However, the above-mentioned prior art has the following problems: firstly, the leakage current from memory cells is increased while on standby. Generally ferroelectric substances tend to be good conductors of leakage current. While power is on, because of the characteristics of SRAMs, either the first node 962 or the second node 963 maintains the supply voltage, and the other maintains the ground voltage. Therefore, the supply voltage is always applied between both ends of the two ferroelectric capacitors 964 and 965 which are connected serially via the ferroelectric polarization control line 966, that is, between the first, and second nodes 962 and 963. This is a cause of the increase in leakage current when memory cells are on standby. Although one of the major features of SRAMs is their low leakage current while on standby, this feature may be lost in the circuit of FIG. 20.
Secondly, there is a problem of increased power consumption when data are written to and read from memory cells. As mentioned above, the two ferroelectric capacitors 964 and 965 are connected between the first and second nodes 962 and 963 via the ferroelectric polarization control line 966. Therefore, these ferroelectric capacitors 964 and 965 write to and read from memory cells using a first bit line 955 and second bit line 956 which has a voltage level opposite to the bit line 955. At this time, because the capacitors serve as parasitic capacitance, an additional electric charge is necessary. This increases the power consumption when data are written to and read from the memory cells.